1. Field of the Invention
The present invention generally relates to a semiconductor package, and more particularly to a semiconductor package including at least one chip capacitor directly mounted on a grounding area of a chip.
2. Description of the Related Art
According to either a single-chip package or a multi-chip package, passive components, such as inductance, resistance and capacitor, are generally integrated with the packaged chip on a substrate or a leadframe, such that the integrated circuit of the package meets the specific electrical requirement. The above-mentioned passive component is mounted on the peripheral area of the substrate or the leadframe outside the chip. For example, the object of installation of a chip capacitor is to connect a power end and a grounding end of a circuit system so as to stabilize the circuit system by means of the decoupling function of the chip capacitor.
Referring to FIG. 1, a conventional semiconductor package 2 includes a chip 10 and a leadframe 20. The leadframe 20 has an unoccupied area 22 which is not occupied by the chip 10. A plurality of chip capacitors 30 are mounted on the unoccupied area 22 of the leadframe 20. A plurality of first bonding wires 12 are used for electrically connecting a plurality of power pads 14 of the chip 10 to power ends 32 of the chip capacitor 30, and a plurality of second bonding wires 34 are used for electrically connecting the power ends 32 of the chip capacitor 30 to a plurality of first leads 24 of the leadframe 20. A plurality of grounding pads (not shown) of the chip 10 are electrically connected to grounding ends 36 of the chip capacitors 30, and the grounding ends 36 of the chip capacitors 30 are electrically connected to a plurality of second leads 26 of the leadframe 20. Referring to FIG. 2, another conventional semiconductor package 50 includes a chip 60 and a substrate 70. The substrate 70 has an unoccupied area 72 which is not occupied by the chip 60. The substrate 70 further has a power ring 74 and a grounding ring 76, wherein the power ring 74 and the grounding ring 76 both are disposed on the unoccupied area 72. A plurality of chip capacitors 80 are mounted on the unoccupied area 72 of the substrate 70 and have power ends 82 and grounding ends 86, wherein the power ends 82 and grounding ends 86 are electrically connected to the power ring 74 and the grounding ring 76, respectively. A plurality of first bonding wires 62 are used for electrically connecting a plurality of power pads 64 of the chip 60 to the power ends 82 of the chip capacitor 80, and a plurality of second bonding wires 66 are used for electrically connecting a plurality of grounding pads 68 of the chip 60 to the grounding ends 86 of the chip capacitors 80. However, the arrangement of above-mentioned conventional semiconductor packages 2, 50 enlarges the size of the whole semiconductor package.
U.S. Pat. No. 5,633,785, entitled “Integrated Circuit Component Package with Integral Passive Component”, discloses an interconnect substrate which is used and a plurality of passive components which are integrally formed therein, incorporated herein by reference. However, it is necessary to have an extra area of substrate for the structure which includes integrated circuit (IC) components integrated with the passive components, wherein the extra area is used for accommodating the passive components, such that the above-mentioned structure is enlarged or more complex, and further the packaging process is more difficult and has a higher cost.
U.S. Pat. No. 6,611,434, entitled “Stacked Multi-Chip Package Structure With On-Chip Integration Of Passive Component”, discloses a stacked multi-chip package, incorporated herein by reference. Passive components of the stacked multi-chip package are mounted on an unoccupied area of the underlying semiconductor chip which is unoccupied by the overlying semiconductor chip, and thus the structure of the whole semiconductor package is tighter in size. However, according to the high density of semiconductor package, the unoccupied area still results in the limit of space.
U.S. Pat. No. 6,005,778, entitled “Chip Stacking And Capacitor Mounting Arrangement Including Spacer”, discloses a multi-chip package, incorporated herein by reference. The multi-chip package includes a first chip, a second chip and a spacer which separates the first chip and second chip. The spacer provides for the first chip grounding in one application and provides for capacitors mounting in another application. The spacer has a top surface and a tiered surface which is electrically connected to the top surface. The passive component is mounted on the top surface of the spacer and has a conductive end and a grounding end which is electrically connected to the top surface. The conductive end and the tiered surface are electrically connected to a grounding pad and a power pad by means of bonding wires, respectively. The grounding pad and power pad are disposed on the first chip and are electrically connected to an external grounding pad and an external power pad by means of bonding wires, respectively. Also, the external grounding pad and external power pad are disposed on the area outside the first chip, such as on a substrate. However, the structure of the above-mentioned multi-chip package is complex and further the packaging process is more difficult and has a higher cost.
Accordingly, there exists a need for a semiconductor package capable of solving the above-mention disadvantages, and the semiconductor package includes at least one chip capacitor directly mounted on a grounding area of a chip and further has a compact structure.